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Integrated Circuit Systems, Inc.
ICS9148-37
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-37 is the single chip clock solution for Desktop/Notebook designs using the VIA MVP3 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS914837 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or the AGP clock frequency(SD_SEL=0)
2
Features
* Generates the following system clocks: - 4 CPU(2.5V/3.3V) upto 100MHz. - 6 PCI(3.3V) @ 33.3MHz - 2AGP(3.3V) @ 2 x PCI - 12 SDRAMs(3.3V) @ either CPU or AGP - 2 REF (3.3V) @ 14.318MHz Skew characteristics: - CPU - CPU<250ps - SDRAM - SDRAM < 250ps - CPU - SDRAM < 250ps - CPU-AGP: < 1ns - CPU(early) - PCI : 1-4ns Supports Spread Spectrum modulation +0.25, 0.6% Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Efficient Power management scheme through PCI and CPU STOP CLOCKS. Uses external 14.318MHz crystal 48 pin 300mil SSOP.
*
* * * * *
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3)
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48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
ICS9148-37
Pin Descriptions
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6,14 7 FS11, 2 PCICLK0 8 10, 11, 12, 13 15, 47 FS2
1, 2
PIN NAME VDD1 REF0 C P U 3 . 3 # _ 2 . 5 1,2 GND X1 X2 VDD2 PCICLK_F
TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT OUT
DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V CPU1. Latched input2 Ground Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU early) Advanced Graphic Por t outputs, powered by VDD4. This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency This asynchronous input halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency SDRAM clock outputs. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequency Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input 24MHz output clock, for Super I/O timing. Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock, for USB timing. Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318MHz reference clock. Latched input at Power On selects either CPU (SDSEL=1) or AGP (SD_SEL=0) frequencies for the SDRAM clock outputs. Supply for AGP (0:1)
PCICLK(1:4) AGP (0:1) CPU_STOP#
1
IN
17 SDRAM 11 PCI_STOP#1 18 SDRAM 10 OUT OUT IN
20, 21,28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25
SDRAM (0:9) VDD3 SDATA SCLK 24MHz MODE1, 2 48MHz
OUT PWR IN IN OUT IN OUT IN OUT PWR OUT IN PWR
26 40, 41, 43, 44 42 46 48
FS01, 2 CPUCLK(0:3) VDDL REF1 SD_SEL VDD4
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9148-37
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# AGP, CPUCLK Outputs Stopped Low Running Running PCICLK (0:5) PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Crystal OSC Running Running Running VCO
0 1 1
1 1 0
Running Running Stopped Low
Running Running Running
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
Functionality
VDD1, 2, 3, 4 = 3.3V5%, VDDL = 2.5V 5% or 3.3 5%, TA= 0 to 70C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU (MHz) 100 95.25 83.3 75 75 68.5 66.8 60 SDRAM (MHz) SD_SEL=1 SD_SEL=0 100 66.6 95.25 63.5 83.3 66.6 75 60 75 75 68.5 68.5 66.8 66.8 60 60 PCI (MHz) 33.3 31.75 33.3 30 37.5 34.25 33.4 30 AG P ( M H z ) 66.6 63.5 66.6 60 75 68.5 66.8 60
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ICS9148-37
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9148-37
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0) Bit Description PWD 0 - 0.25% Spread Spectrum Modulation Bit 7 1 - 0.6% Spread Spectrum Modulation 0 Bit6 Bit5 CPU Clock PCI AGP Bit4 111 100 33.3 66.6 110 95.25 31.75 63.5 Bit 101 83.3 33.3 66.6 Note 6:4 100 75 30 60 1 011 75 37.5 75 010 68.5 34.25 68.5 001 66.8 33.4 66.8 000 60 30 60 0 - Frequency is selected by hardware Bit 3 select, ched Inputs 0 Lat 1 - Frequency is selected by Bit 6:4 (above) 0 - Spread Spectrum center spread type. 0 1 - Spread Spectrum down spread type. 0 - Norm Bit 1 1 - Spreaal Spectrum Enabled 0 d 0 Ru ing Bit 0 1- -Tristnne all outputs 0 at
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) CPUCLK3 (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 15 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description (Reserved) PCICLK_F (Act/Inact) AGP0 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
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ICS9148-37
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 17 18 20 21 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 46 2 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) AGP1(Act/Inact) (Reserved) (Reserved) REF1 (Act/Inact) REF0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
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ICS9148-37
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-37. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-37. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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ICS9148-37
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-37. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-37 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9148-37
Shared Pin Operation Input/Output Pins
Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-37 serve as dual signal functions to the device. During initial powerup, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device's internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
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ICS9148-37
Fig. 2a
Fig. 2b
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ICS9148-37
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . 7.0 V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 VDD + 0.3 V VSS - 0.3 0.8 V Input Low Voltage VIL Input High Current I IH VIN = V DD 0.1 5 mA VIN = 0 V; Inputs with no pull-up resistors -5 2.0 mA Input Low Current IIL1 Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 -100 mA 100 160 mA Operating I DD3.3OP CL = 0 pF; 66.8 MHz Supply Current VDD = 3.3 V; 14.318 MHz Input frequency Fi Input Capacitance1 CIN Logic Inputs 5 pF X1 & X2 pins 27 36 45 pF CINX Transition Time1 Ttrans To 1st crossing of target Freq. 2 ms Settling Time1 Ts From 1st crossing to 1% target Freq. ms Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. 2 ms Skew1
1
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads TCPU-PCI1 VT = 1.5 V; CPU Leads TCPU-AGP VT = 1.5 V; CPU Leads
-500 1 -1
200 2.8 0
500 4 1
ps ns ns
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1
1
SYMBOL CONDITIONS CL = 0 pF; 66.8 MHz I DD2.5OP TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Lead TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
MIN
TYP 10 200 2.7
MAX 20 500 4
UNITS mA ps ns
-500 1
Guaranteed by design, not 100% tested in production.
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ICS9148-37
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V Rise Time VOL = 0.4 V, VOH = 2.0 V tr2B1 1 Fall Time VOH = 2.0 V, VOL = 0.4 V tf2B 1 Duty Cycle VT = 1.25 V dt2B Skew tsk2B1 VT = 1.25 V Jitter, Single Edge tjsed2B1 VT = 1.25 V Displacement2 Jitter, One Sigma tj1s2B 1 VT = 1.25 V Jitter, Absolute tjabs2B1 VT = 1.25 V
1 2
MIN 2
19
40
TYP 2.2 0.3 -20 26 1.5 1.6 47 60 200 65 160
MAX 0.4 -16 1.8 1.8 55 250 250 150 300
UNITS V V mA mA ns ns % ps ps ps ps
-300
Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2A VOL2A IOH2A IOL2A tr2A1 tf2A1 d t2A1 tsk2A1 t j1s2A1 tjabs2A1
CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.5
33
TYP 2.6 0.35 -29 37 1.75 1.1
MAX 0.4 -23 2 2 55 250 150 250
UNITS V V mA mA ns ns % ps ps ps
45
50 50 65
-250
165
Guaranteed by design, not 100% tested in production.
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ICS9148-37
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -28 mA Output High Voltage VOH1 IOL = 23 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 1 Rise Time Tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 Tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 Skew
1 1
MIN 2.4
41
TYP 3 0.2 -60 50 1.75 1.5
MAX 0.4 -40 2 2 55 500 150 +250 400
UNITS V V mA mA ns ns % ps ps ps ps
Dt1 Tsk1 Tj1s1 Tjabs1 Tjabs1
VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (with synchronous PCI) VT = 1.5 V (with asynchronous PCI)
45
50 200 50
Jitter, One Sigma Jitter, Absolute1 Jitter, Absolute1
1
-250 -400
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.8 1.6
MAX 0.4 -40 2 2 55 250 150 250 250 650
UNITS V V mA mA ns ns % ps ps ps ps ps
d t1
45
51 130 40 200
tsk1 1 tj1s1a tj1s1b tabs1a tjabs1b
1
-250 -650
135 500
Guaranteed by design, not 100% tested in production.
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ICS9148-37
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma1 Jitter, Absolute1
1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous VT = 1.5 V, asynchronous
MIN 2.4
41
TYP 3 0.2 -60 50 1.1 1
MAX 0.4 -40 2 2 55 250 3 5 6
UNITS V V mA mA ns ns % ps % % %
d t1 1 tsk1
1
45
49 130 2
tj1s1 tabs1a tjabs1b
-5 -6
2.5 4.5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 2.6 0.3 -32 25 2 1.9
MAX 0.4 -22 4 4 57 3 5
UNITS V V mA mA ns ns % % %
d t5 1 tj1s5 tjabs5 1
1
45 -5
54 1 -
Guaranteed by design, not 100% tested in production.
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ICS9148-37
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended.
Connections to VDD:
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ICS9148-37
N
c
300 mil SSOP SYMBOL A A1 b c D E E1 e h L N a VARIATIONS N D mm. MIN 15.75 MAX 16.00 MIN .620 D (inch) MAX .630 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
L
INDEX AREA
E1
E
12 D h x 45
A A1
-Ce
b SEATING PLANE .10 (.004) C
48
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9148yF-37 LF-T
Example:
ICS XXXX y F PPP LF- T
Designation for tape and reel packaging Lead Free (Optional) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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